A couple of weeks back I started designing my own CPU (called Bizzas CPU) in Quartus II with the initial goal of getting it running on an FPGA. Right now im bouncing between many different tasks as well as trying to just chillax from time to time.
Elements of a CPU such as registers, program counters and ALU‘s are pretty easy to design. I have most of that done. My current task is to design a robust and efficient instruction decoder, or instruction executor as I call it. After that, I will make an instruction loader.
Once those are done, the CPU will hopefully be ready to run inside the FPGA without any significant connections to the outside world. Then the next step is to wire it up to some memory and other peripherals, maybe even make a VGA interface.
End goal is ofcourse world domination!
Here is what a 1-bit ALU block looks like inside:
This particular configuration can do add, subtract, XOR, AND and OR. Not bad for only 7 logic gates.
My project is shared in its entirety on GitHub: https://github.com/joonicks/BizzasCPU
Just arrived from China, a small cheap FPGA: Altera Cyclone-II (EP2C5T144).
The device itself is the least capable of all the Cyclone II FPGAs, but its seriously cheap at only $13. And its big enough to hold a basic CPU core. This is what it looks like (9V battery included for scale):
The USB Blaster has to be bought separately but only costs an additional $3. Unfortunatly the DC jack is for 5V, its unregulated unlike Arduinos. Bummer. And I dont have any 5V adapter with a 5.5mm plug so I have to make one myself.
Here are the specs for the board itself (and others of the same family, its the smallest one, EP2C5):
So now Im mostly ready to start designing and testing my own CPU. Ive already started some basic designing since a couple of nights back. Gaining some insights and making early design choices.
I still havent committed to wether the data bus should be 8-bit or 16-bit. Id like to make it 16-bit but that means a whole lot of wires (since its ultimately imagined as a breadboard design). Now that I think of it maybe I should make a first test design with address bus and data bus both being 8-bit.