BizzasCPU springs to life

Around the beginning of September, I resumed work on my old CPU project that had been collecting dust on github. After about 10 days work, I reached a point where I started implementing the logic for instruction execution.

The more simple instructions were all added and verified quite quickly. Last ones to be implemented were JMP and memory access instructions. JMP instructions actually turned out to be extraordinarily simple logic.

It currently compiles into less than 300 logic elements, so it is a very simple (8-bit data, 16-bit address) CPU design.

Here is what it looks like running in simulation software:

It still hasnt been tested on FPGA hardware, hopefully that day will come before more years pass. I just ordered a Terasic DE10-Nano which has more test hardware built onto it, which should make debugging easier.

For more details on BizzasCPU, check out the github repository:

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